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Final Electrical Specifications
LT3804 Secondary Side Dual Output Controller with Opto Driver
FEATURES
s s
DESCRIPTIO
June 2003
s s s s s s
Regulates Two Secondary Outputs Optocoupler Feedback Driver and Second Output Synchronous Driver Controller True Differential Remote Sensing Regulation High Switching Frequency: up to 800kHz Programmable Current Limit Programmable Soft-Start and Power Good Automatic Frequency Synchronization Available in Thermally Enhanced 28-Lead TSSOP
The LT(R)3804 is a high efficiency step-down switching regulator with optocoupler feedback control for regulating multiple outputs in single-secondary winding isolated power supplies. The LT3804 contains an error amplifier and an optocoupler driver to regulate the first (main) output. For the second output regulation, the LT3804 contains a complete PWM controller to drive dual synchronous N-channel MOSFETs. With leading edge modulation, it operates with either current or voltage mode control of the primary side. The LT3804 is synchronized to the falling edge of the transformer secondary winding and can be used in singleended or double-ended isolated power converter topologies. A user selectable discontinuous conduction mode improves light load efficiency. True differential Kelvin sensing is used for each output feedback amplifier to achieve high regulation accuracy and design simplicity. Other features include soft start, current limit and power good flags.
APPLICATIO S
s s s s
48V Input Isolated DC/DC Converters Multiple Output Power Supplies Offline Converters DC/DC Power Modules
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATIO
VIN 36V TO 72V
VCC BIAS
L1 1.8H
0.003 LT3804 SYNC CL1N CL1P VCC CSET 390pF PGND TGATE SW BGATE Q2 x2 Q1 L2 1.8H 0.003
*
*
Q4
OUT2 LTC1693-1
Q3 x2
OUT1 IN1 IN2
VOS1- TG BG
GNDS1 604 CL2P CL2N VAOUT2 2.74k VFB1 VFB2 VAOUT1 OPTO GNDS2
3804 F01
*
*
VOS1+
LT3781 SG
*
VC + - VREF VFB
*
1.5k
ISOLATION BOUNDARY
COUT1, COUT2: SANYO POSCAP 4TPE680MF 680F/4V L1, L2: SUMIDA CEP125-IR8MC-H Q1-Q4: SILICONIX Si7892DP
Figure 1. 250kHz, 3.3V and 1.8V Output Isolated DC/DC Converter (Simplified Schematic)
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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VOS1+ VOS1-
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+
VOUT1 3.3V AT 15A COUT1
+
VOUT2 1.8V AT 15A COUT2
3.01k
1
LT3804
ABSOLUTE
(Note 1)
AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW CL1P CL1N ILCOMP2 BOOST TGATE SW CSET SYNC SS2 1 2 3 4 5 6 7 8 9 29 28 ILCOMP1 27 GBIAS 26 BGATE 25 VCC 24 PGND 23 OPTO 22 VAOUT1 21 CL2N 20 CL2P 19 PGOOD 18 VFB1 17 SS1 16 BGS 15 VAOUT2
VCC Supply Voltage .................................................. 26V BOOST Pin Voltage with Respect to SW Pin ............ 10V BOOST Pin Voltage with Respect to GND Pin .......... 35V SYNC Pin Voltage (Note 2) ..................................... 30V GNDS1 Pin Voltage ................................................... 1V GNDS2 Pin Voltage ................................................... 1V Operating Junction Temperature Range LT3804E (Note 3) ..............................-40C to 125C Storage Temperature Range ..................-65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LT3804EFE
PGIN1 10 PGIN2 11 GNDS2 12 GNDS1 13 VFB2 14
FE PACKAGE 28-LEAD PLASTIC TSSOP
TJMAX = 125C, JA = 38C/W EXPOSED PAD IS SGND (PIN 29) MUST BE CONNECTED TO PCB
Consult LTC Marketing for parts specified with wider operating temperature ranges.
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 11V, GNDS1=GNDS2=0V, operating maximum VCC = 25V, no load on any outputs, unless otherwise noted.
PARAMETER Overall Supply Voltage (VCC) Supply Current (IVCC) BOOST Pin Current CONDITIONS
q
ELECTRICAL CHARACTERISTICS
MIN 8
TYP
MAX 25 13 3 3 0.609 0.609 3 0.5 -100
UNITS V mA mA mA V V mV A A V V V V V A A dB MHz A
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VAOUT2 1.2V (Switching Off) VBOOST = VSW + 8V, 0V VSW 24V TGATE High TGATE Low Common Mode: 20mV (0C to 125C) (-40C to 125C) VREF over Common Mode: 100mV VFB1 = VREF1, VFB2 = VREF2 -100mV GNDS1, GNDS2 100mV VFB1 = VREF1 - 10mV, I VAOUT1 = -50A VFB1 = VREF1 - 10mV, I VAOUT1 = -50A VFB1 = VREF1 + 10mV, I VAOUT1 = 100A VFB2 = VREF2 - 10mV, I VAOUT2 = -50A VFB2 = VREF2 + 10mV, I VAOUT2 = 100A 0.591 0.587 -3
9 2 2 0.6
Voltage Amplifier VA1,VA2 Reference Voltage (VREF1,VREF2)
q
VFB1, VFB2 Pin Input Current Remote Ground Pin (GNDS1,GNDS2) Current VAOUT1 High at OA1 Threshold 1.5V VAOUT1 High at OA1 Threshold 1.25V VAOUT1 Low VAOUT2 High VAOUT2 Low VAOUT1 Source Current VAOUT2 Source Current Open-Loop Gain Gain Bandwidth Product Soft-Start Current (SS1,SS2)
q
q q
100 70
0.2 -50 1.75 1.45 0.7 4.5 0.8 230 150 100 10 10
400 250
5
24
2
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W
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WW
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LT3804
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 11V, GNDS1=GNDS2=0V, operating maximum VCC = 25V, no load on any outputs, unless otherwise noted.
PARAMETER Opto Driver Amplifier OA1 OA1 Upper Threshold OA1 Threshold Hysteresis OA1 Voltage Gain (VOPTO/VAOUT1) VOPTO High VOPTO Low IOPTO Short-Circuit Current Limit Power Good Power Good Window Threshold (PGIN1-GNDS1, PGIN2-GNDS2) Input Current (PGIN1,PGIN2) Delay Time for Power Bad Output Low (PGOOD) Current Limit Amplifier CA1, CA2 Current Limit Threshold (CL1P-CL1N, CL2P-CL2N) BGATE Off Threshold at (VCL2P-VCL2N), BGS Pin Float Switching Off Threshold at ILCOMP2 Input Current (CL1P, CL1N, CL2P, CL2N) Oscillator Switching Frequency CS = 500pF (NO SYNC) CS = 333pF (NO SYNC) CS = 200pF (NO SYNC) CS = 500pF CS = 333pF CS = 200pF CS = 1000pF (NO SYNC) CS = 1000pF (NO SYNC) Falling Edge VSYNC VFB2 = VREF2 - 5mV, CS > 333pF IGBIAS < 25mA ITGATE < 50mA, VBOOST = VGBIAS - 0.5V IBGATE < 50mA ITGATE < -50mA IBGATE < 50mA 10nF Load 1nF Load
q q q q q q q q q q q
ELECTRICAL CHARACTERISTICS
CONDITIONS
MIN 1.4 5.6 4.5 0 -50
TYP 1.55 0.25 6 5.2 0.1 -25
MAX 1.65 6.4 6 0.25 -12
UNITS V V V V V mA
1.2V < VOPTO < 4V, ROPTO = 1k VAOUT1= 0.9V, IOPTO = -10mA VFB1 = VREF1 - 10mV, ROPTO = 1k VFB1=VREF1 - 10mV, GNDS1 = 0V, VOPTO = 4V
q q q q
-100mV < GNDS1, GNDS2 < 100mV 0V < PGIN1, PGIN2 < 1V 25mV Overdrive on PGIN1,PGIN2 2mA into the Pin Common Mode Voltage from 0V to VCC - 2.5V VAOUT1 = 1.2V, VAOUT2 = 2.5V, Commond Mode Voltage from 0V to VCC - 2.5V VILCOMP2 VCL2P = VCL1N, VCL2P = VCL2N
q q
0.85 0.2 100 200 150
1.15 0.35 300 300
VREF A s mV
q
40 0
50 8 100
60 15 0.15
mV mV V A
170 240 400 245 345 575 0.90
200 280 470
240 340 570 400 500 800
kHz kHz kHz kHz kHz kHz V V V %
Synchronization Frequency Range
CSET Ramp Valley Voltage CSET Peak-to-Peak Voltage Synchronization Pulse Threshold on SYNC Pin Maximum Duty Cycle Gate Drivers (TGATE, BGATE) VGBIAS VTGATE High (VTGATE - VSW) VBGATE High VTGATE Low (VTGATE-VSW) VBGATE Low Peak Gate Drive Current Gate Drive Rise and Fall Time
1.15 2.4 2.5
1.4
75 7.5 5 5
80 8 6 6 8.5 7.5 7.5 0.5 0.5 1 25
q
V V V V V A ns
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: If highter than 30V on SYNC pin is needed, add a 10k resistor in series with the pin.
Note 3: The LT3804E is guaranteed to meet performance specifications from 0C to 70C. Specifications over the - 40C to 85C operating temperature range are assured by design, characterization and correlation with statistical process controls.
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LT3804 TYPICAL PERFOR A CE CHARACTERISTICS
VGBIAS vs IGBIAS Over Junction Temperature
8.1 -40C 12 8.0
VGBIAS (V)
25C
GAIN (dB)
ICC (mA)
7.9
7.8 125C 7.7 0 10 IGBIAS (mA) 20 26
3804 G01
VREF vs VCC, FREQ vs VCC
3 VREF (mV) 2 FREQUENCY (kHz) 1 0 -1 FREQ 1 0 -1 10 15 VCC (V) 20 25
3804 G04
CSET = 500pF TA = 25C
0.85 400 0.80 0.75 200 0.70
VREF (V)
VREF
Switching Frequency vs Temperature
CSET = 500pF
SWITCHING FREQUENCY (kHz)
215 210
IGBIAS (mA)
VAOUT2 (V)
205 200 195
50 100 -40 -20 25 75 0 JUNCTION TEMPERATURE (C)
4
UW
3804 G07
ICC vs VCC (Switching Off)
13 TA = 25C 120
Voltage Amplifier VA1, VA2 Gain and Phase
TA = 25C GAIN (-111) PHASE 40 -100 -0
11 10 9 8 7
80
-50 PHASE (DEG)
0 6 5 -20 8 10 12 14 16 18 VCC (V) 20 22 24 10 100 1k 10k 100k 1M FREQUENCY (Hz) 0dB, 10MHz
-150 -180 10M 100M
3804 G03
3804 G02
CSET vs Switching Frequency
TA = 25C 800 CSET 0.95 600 MAXIMUM DUTY CYCLE 0.90 MAXIMUM DUTY CYCLE 1.00 0.602 0.601 0.600 0.599 0.598 0.587
VREF vs Temperature
FREQ (kHz)
100 200 300 400 500 600 700 800 900 1000 CSET (pF)
3804 G05
0.596 50 100 -40 -20 25 75 0 JUNCTION TEMPERATURE (C)
125
3804 G06
GBIAS vs IGBIAS (Charging 2.2F)
8 300 250 200 150 100 50 0 125 0 500s TIME IGBIAS CGBIAS = 2.2F TA = 25C VGBIAS 12 10 8 6 4 2 0 1ms
3804 G08
Current Limit Amplifier CA1 Gain at VCC = 11V, VCL2N = 5V
7 6 5 4 3 2 CSET VALLEY 1 0 30 40 50 60 VCL2P - VCL2N (mV) 70
3804 G09
VCC = 11V VCL2N = 5V TA = 25C
VGBIAS (V)
CSET PEAK
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LT3804
PI FU CTIO S
CL1P (Pin 1): Current Limit Amplifier CA1 Positive Input. CA1 drives optocoupler when the first output is in current limit.The threshold is set at 50mV. CL1N (Pin 2): Current Limit Amplifier CA1 Negative Input. When used, CL1N is connected to the output, and CL1P is connected to the other end of the output current sense resistor. ILCOMP2 (Pin 3): Current Limit Amplifier CA2 Compensation Node. At second output current limit, CA2 pulls down on this pin to regulate output current. BOOST (Pin 4): Topside (Boosted) Driver Supply.This pin is used to bootstrap and supply the topside power switch gate drive circuitry. In normal operation VBOOST is powered from the internally generated 8V GBIAS; VBOOST = VSW + 8V when TGATE is on. TGATE (Pin 5): Topside (Boosted) N-Channel MOSFET Driver. When TGATE is on, the voltage is equal to VSW + 6V. SW (Pin 6): Switch Node Connection to Inductor. CSET (Pin 7): Oscillator Frequency Setting Pin.The capacitor from this pin to ground sets the PWM switching frequency. SYNC (Pin 8): Synchronization Input. This pin should be connected to the secondary side output of the power transformer with a series resistor. A filtering capacitor of 10pf is recommended. SS2 (Pin 9): Soft-Start for the Second Output. A capacitor on this pin sets the output ramp-up rate. The typical time for SS2 to reach the programmed level is: (C * 0.6V)/10A. PGIN1 (Pin 10): First Output Power Good Input.The voltage setting resistor divider should be connected to GNDS1 if remote sensing is used. PGIN2 (Pin 11): Second Output Power Good Input. The voltage setting resistor divider should be connected to GNDS2 if remote sensing is used. GNDS2 (Pin 12): Second Output Remote Ground Sensing. GNDS1 (Pin 13): First Output Remote Ground Sensing. VFB2 (Pin 14): Voltage Amplifier VA2 Inverting Input. A resistor divider to this pin sets the second output voltage. The reference voltage at this pin is VREF2 (0.6V referred to remote sensing ground GNDS2). VAOUT2 (Pin 15): Voltage Amplifier VA2 Output.
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BGS (Pin 16): Bottom Gate Switching Control. CA2 monitors the inductor current and prohibits BGATE from turning on when the inductor current is low (below 8mV across the current sense resistor RS2) allowing discontinous mode operation and avoiding reverse inductor current. Grounding BGS disables this function, so that the PWM is always in continuous mode except during start-up. SS1 (Pin 17): Soft-Start for the First Output. A capacitor on this pin sets the output ramp-up rate. The typical time for SS1 to reach the programmed level is: (C * 0.6V)/10A. VFB1 (Pin 18): Voltage Amplifier VA1 Inverting Input. A resistor divider to this pin sets the first output voltage. The reference voltage at this pin is VREF1 (0.6V referred to remote sensing ground GNDS1). PGOOD (Pin 19): Power Good. PGOOD goes high to indicate power good only when both PGIN1 and PGIN2 sense power good. A pull up resistor is required on this pin if the power good function is used. CL2P (Pin 20): Second 0utput Current Limit Amplifier CA2 Positive Input.The threshold is set at 50mV. CL2N (Pin 21): Current Limit Amplifier CA2 Negative Input. When used, CL2N is connected to the output capacitor, and CL2P is connected to the other end of the output current sense resistor. VAOUT1 (Pin 22): Voltage Amplifier VA1 Output. OPTO (Pin 23): Optocoupler Driver. A resistor to the opto diode is required to set the optocoupler bias current. Maximum sourcing current is 10mA at 5V. PGND (Pin 24): Ground of the Bottom Side N-Channel MOSFET Driver. VCC (Pin 25): Supply of the Chip. A low ESR capacitor is required to bypass the supply. BGATE (Pin 26): Bottom Side N-Channel MOSFET Driver. GBIAS (Pin 27): 8V Regulator Output for Boostrapping VBOOST. A bypass capacitor of at least 2F is needed. ILCOMP1 (Pin 28): Current Limit Amplifier CA1 Compensation Node . When the first output is in current limit, CA1 pulls down VAOUT1 pin to regulate the first output current. Exposed Pad (Pin 29): Signal Ground. Must be electrically connected on PCB.
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LT3804
BLOCK DIAGRA
VOUT1
M4 90k SS1 17 TGATE 1.3V 4 BOOST D14 10A VREF1 0.6V 15k
- VA1 + C9 Q2 200s DELAY
+
LT3781 A3 BGATE R1 6 + A10 A8 SW A4 5
CSS1 1F M1 -
ROPTO
VCC 2.5V SW
+ + +
8V 27 GBIAS -
Q3
OPTO
+
3.5V A6 A13 R2 2V 200A 7V
R11 OPTO A11
ISOLATION BOUNDARY SS2
+
R S 1.6V
PWM A7 SYNC 8 A1 OSC - E4 + ONE SHOT A2 2.5V - +
C16 -+
1.1 VREF2 0.9 VREF2
+
8mV - CA2 +
CS 10pF
+
+
50mV
CSET 7
D6 - VA2 + NOTE: PACKAGE BOTTOM METAL PLATE IS FUSED TO SIGNAL GROUND. AGND 29 EXPOSED PAD 9 CSS2 1F SS2 D7 10A 1.3V
+
-
+
RS 10k
-
-
+
-
+
-
+
+
-
OPTO 23 0.9VREF1 + +
OA1 Q5 D15
1.5V/ 1.2V VTH
19 PGOOD
VOUT2 L1 RS2
C3 2F BGATE 26 24
C2 0.3F
R3
R19 LOAD
M2 PGND 16 BGS 11 PGIN2
COUT2
R4
R20
C14 PGOOD C15 200s DELAY 20 21 3 15 14 VREF2 0.6V 12 GNDS2
3804 BD
Q4 CL2P CL2N ILCOMP2 VAOUT2 VFB2 R6, 5k C6, 100pF
W
8V
1.1VREF1 -
+
C13
+
SHUTDOWN +- CA1 CA +
6
L2 RS1 C17 200pF R13 R16 LOAD Q1 D2 VCC 25 22 18 10 PGIN1 13 50mV - E2 ILCOMP1 CL1P CL1N 28 1 2 VFB1 GNDS1 VAOUT1 C12 500pF R12 R14 R17 COUT1
TRANSFORMER SECONDARY OUTPUT
R7
R8
VIN 36V TO 72V
C8
M3
+
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LT3804
OPERATIO
To generate isolated multiple outputs, most systems use either multiple secondary windings or cascade regulators for each additional output. Multiple secondary windings sacrifice regulation of the auxiliary outputs. Cascaded regulators require a larger inductor for the main output, because all of the power is processed in series. By generating the auxiliary output(s) from the secondary winding of the main output, the LT3804 allows for parallel processing of the output power. This minimizes the main output inductor size and directly regulates the auxiliary output. With synchronous rectification, the system efficiency is greatly improved. The LT3804 regulates both the main and one auxiliary output, with true remote sensing to achieve high output accuracy. To regulate the first output, the LT3804 contains a high gain error amplifier VA1 and an optocoupler driver OA1 with a unique feature that reduces output overshoot to a minimum. For details see the Applications Information section. The second output includes a voltage amplifier, VA2, (see Block Diagram)a voltage mode PWM with trailing edge synchronization and leading edge modulation, a current limit amplifier, CA2, and high speed synchronous switch drivers.
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During normal operation (see Figure 2), a switching cycle begins at the falling edge of the transformer secondary voltage VS. The internal oscillator is reset, turning off the top MOSFET, M1, and turning on the bottom MOSFET, M2. During this portion of the cycle, the inductor current is discharged by the output voltage VOUT2. The transformer secondary voltage, VS, will go high during this portion of the cycle. Since M1 is off, the switch node voltage, VSW, remains zero. The inductor current continues to be discharged by the output voltage VOUT2. This condition lasts until the ramp signal intersects the feedback error amplifier output VAOUT2. The top MOSFET M1 turns on, pulling the switch node voltage to VS. The inductor current of the LT3804 circuit is then charged by VS - VOUT2. The effective on time of this buck circuit ends when the secondary voltage becomes zero. The next cycle repeats. The ideal equation for duty cycle of the LT3804 is: D2 = VOUT2/VSP where VOUT2 is the auxiliary output voltage, VSP is the amplitude of the secondary voltage and D2 is the duty cycle of the switching node voltage VSW, as defined in Figure 2.
VRESET T D1T TRANSFORMER SECONDARY VOLTAGE SYNC SIGNAL VRESET VS VSP RAMP VCSET VAOUT2 TGATE BGATE IL2 T SWITCH NODE VSW D2T VSP
3710 F02
Figure 2. Leading Edge Modulation, Trailing Edge Synchronization
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LT3804
APPLICATIO S I FOR ATIO
Synchronization and Oscillator Frequency Setting The switching is synchronized to the secondary winding falling edge and the synchronization threshold is typically 2.5V. The synchronization falling edge triggers an internal inverted ramp (see Figure 2) and starts a new switching cycle for the leading edge voltage mode PWM. The reason for using leading edge modulation is to leave the transformer primary side peak current sensing undisturbed. For proper synchronization, the oscillator frequency should be set lower than the system switching frequency with tolerances taken into account. fOSC < (fSL * 0.8) fSL is the low limit of the system switching frequency and 0.8 is the tolerance of fOSC. For example, given a system operating at 200kHz with 15% tolerance, then fSL = 200kHz * 85% = 170kHz; and fOSC < (170kHz * 0.8), so fOSC should be set below 136kHz. Once fOSC is determined, CSET can be calculated by CSET = (103540pF/fOSC(kHz)) - 18pF. For fOSC = 200kHz, CSET = 500pF. Output Voltage Programming The LT3804 uses true remote sensing (separate ground sensing pins, GNDS1 for the first output and GNDS2 for the second output) to eliminate output error pickup due to parasitic resistance. The feedback reference voltages VREF1 and VREF2 are 0.6V referred to GNDS1 and GNDS2 respectively. The output voltage can be easily programmed by a resistor divider, as shown in the Block Diagram: VOUT1 = 0.6 (1 + R13/R14) VOUT2 = 0.6 (1 + R3/R4) where R14 connects to GNDS1 and R4 connects to GNDS2.
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For accurate sensing results, GNDS1 and GNDS2 should stay within -0.1V and 0.1V referred to GND. Note that if either GNDS1 or GNDS2 is not connected, the LT3804 will be shut down. Power Good When both outputs reach between 90% and 110% of the programmed level, VPGOOD goes high( a pull-up resistor is required if the function is used) to signal power good. If either output rises above 110% or drops below 90%, VPGOOD goes low after a 200s delay. PGIN1 senses the first output and PGIN2 senses the second output with a resistor divider. PGIN1 and PGIN2 are compared to the references VREF1 and VREF2 respectively. Resistor dividers should be connected to GNDS1 and GNDS2 with respect to each output. Current Limit CA1 The first output current limit is set by the 50mV threshold across CL1P and CL1N, the inputs of the amplifier CA1. By connecting an external resistor RS1(see Block Diagram), the current limit is set for 50mV/RS1. C17 on ILCOMP1 stablizes the current limit loop. If current limit is not used, both CL1P and CL1N should be grounded and C17 is not needed. Current Limit CA2 The second output current limit is set by the 50mV threshold across CL2P and CL2N, the inputs of the amplifier CA2. By connecting an external resistor RS2 (see Block Diagram), the current limit is set for 50mV/RS2. R6 and C6 on ILCOMP2 stablize the current limit loop. If current limit is not used, both CL2P and CL2N should be grounded and the BGS pin should also be grounded to disable comparator CA2; R6 and C6 are not needed.
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LT3804
APPLICATIO S I FOR ATIO
Filtering on the SYNC Input
A small RC filter with RS = 10k and CS = 10pF is necessary on the SYNC pin to eliminate fast switching glitches caused by coupling from external components and layout parasitics. Optocoupler Driver Optocoupler driver OA1 is an amplifier with a fixed gain of 6 and can source up to 10mA into the optocoupler. An external resistor is needed from the OPTO pin to the optocoupler for DC biasing the optocoupler. With a unique 0.3V hysteresis on the threshold VTH, OA1 turns into a comparator when it detects output startup or output short. This comparator action jumpstarts the optocoupler to reduce the output overshoot drastically (see Figure 3). Soft-Start and Shutdown First Output During soft-start, VSS1 is the reference voltage that controls the output voltage, so the output ramps up following VSS1. The effective range of VSS1 is from 0V to VREF1. The typical time for the output to reach the programmed level is: t = (CSS1 * 0.6V)/10A
22nF
470 3.3V VOUT1
VAOUT1
VFB1
OA1
15k VA1
1k ROPTO OPTO 90k
VREF1 0.6V LT3804
+
-
OPTO
1.5V/ 1.2V VTH
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To shut down the first output, the SS1 pin should be pulled below 50mV by a small signal VN2222 type N-channel MOSFET. Soft-Start and Shutdown Second Output During soft-start, VSS2 is the reference voltage that controls the output voltage, so the output ramps up following VSS2. The effective range of VSS2 is from 0V to VREF2. The typical time for the output to reach the programmed level is: t = (CSS2 * 0.6V)/10A During start up, BGATE will stay off until VSS2 reaches 1.6V. This prevents the bottom MOSFET from turning on if the output is precharged. To shut down the second output, the SS2 pin should be pulled below 50mV by a small signal VN2222 type N-channel MOSFET. Note that during shutdown BGATE will be locked off when VSS2 drops below 0.6V. This prevents the bottom MOSFET from discharging the output, which could cause the output to undershoot below ground.
VOUT1 5nF 1k R13 2.7k VOUT1 SHORT STARTUP OR SHORT RELEASE 1.7V VAOUT1 R14 600 VTH 1.4V 1.5V 1.2V 2V 0V
3804 F03
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VOPTO GNDS1
Figure 3. Optocoupler Driver
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LT3804
APPLICATIO S I FOR ATIO
Output Inductor Selection The key parameters for choosing the inductor include inductance, RMS and saturation current ratings, and DCR. The inductance must be selected to achieve a reasonable value of ripple current, which is determined by: IL = VOUT * (1 - D) f *L
Where VOUT is the output voltage, D is the duty cycle, f is switching frequency and L is the inductance. Typically, the inductor ripple current is designed to be 20% to 40% of the maximum output current. The RMS current rating must be high enough to deliver the maximum output current. A sufficient saturation current rating should prevent the inductor core from saturating. These two current ratings can be determined by:
I IRMS IO + LMAX 12 I ISAT IO + LMAX 2
2
2
where IO is the maximum DC output current and ILMAX is the maximum peak-to-peak inductor ripple current. To optimize the efficiency, we usually choose the inductor with the minimum DCR if the inductance and current ratings are the same. Output N-Channel MOSFET Drivers The LT3804 employs high speed N-channel MOSFET synchronous drivers to achieve high system efficiency. GBIAS is the 8V regulator output to bias and supply the drivers and should be properly bypassed with a low ESR
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capacitor to the ground plane. A Schottky catch diode is required on the switch node. Power MOSFET Selection The LT3804 drives two external N-channel MOSFETs to deliver high currents at high efficiency. The gate drive voltage is typically 6.5V. The key parameters for choosing MOSFETs include drain to source voltage rating VDSS and RDS(ON) at 6.5V gate drive. Note that the transformer secondary voltage waveform will overshoot at its rising edge due to the ringing between transformer leakage inductance and parasitic capacitance. The VDSS of both top and bottom MOSFETs must be sufficiently higher than the maximum overshoot. It is recommended that an RC snubber or voltage clamping circuitry be placed across the transformer secondary winding to limit the VS overshoot. The RDS(ON) of the MOSFETs should be selected to deliver the required current at the desired efficiency as well as to meet the thermal requirement of the MOSFET package. The conduction power losses of the MOSFETs are: PM1 IO2 * RDS(ON)M1 * D PM2 IO2 * RDS(ON)M2 * (1 - D) where IO is the maximum output current of LT3804 circuit, and RDS(ON)M1 and RDS(ON)M2 are the on-resistance for the top and bottom MOSFETs, respectively. The RDS(ON) must be determined with 6.5V gate drive at the expected operating temperature. Numerous high performance power MOSFETs are available from Siliconix, International Rectifier and Fairchild. If the VDSS and RDS(ON) ratings are the same, the MOSFETs with the lowest gate charge QG should be chosen to minimize the power loss associated with the MOSFET gate drives, the switching transitions, and the controller bias supply.
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LT3804
APPLICATIO S I FOR ATIO
Light Load Operation of Second Output
If the BGS pin is grounded, the LT3804 stays in continuous mode independent of load condition except during softstart operation (see the Soft-Start section). If the BGS pin is left open under light load, VRS2 will drop below 8mV, BGATE will be turned off(see comparator CA2 of Block Diagram), and the LT3804 will enter discontinous mode operation. Second Output Capacitor Selection The selection of the output capacitor is determined by the output ripple and load transient requirements. In low output voltage applications, always choose capacitors with low ESR. The output ripple voltage is approximated by:
1 VOUT IL ESR + 8fC OUT
where IL is the inductor peak-to-peak ripple current. A partial list of low ESR high performance capacitor types includes SP capacitors from Panasonic and Cornell Dubilier, POSCAPs and OS-CON capacitors from Sanyo, T510 and T520 surface mount capacitors from Kemet. Layout Considerations For maximum efficiency, the switching rise and fall times should be less than 20ns. To prevent radiation, the power MOSFETs, SW pin and input bypass capacitor leads should be kept as short as possible. A ground plane should be used under the switching circuitry to prevent interplane coupling and to act as a thermal spreading path. Note that the bottom metal of the package is the heat sink as well as the IC signal ground, and must be soldered to the ground plane.
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Design Example Figure 4 shows an application example of LT3804. It is a dual output high efficiency isolated DC/DC power supply with 36V to 72V input range, 3.3V/15A and 1.8V/15A outputs. The basic power stage topology is a two-switch forward converter with synchronous rectification. The primary side controller uses an LT3781, a current mode two-switch forward controller with built-in MOSFET drivers. On the secondary side, the LT3804 is used to provide the voltage feedback for the 3.3V output. The output from the built-in optocoupler driver is fed into an optocoupler (MOC207) and then transferred to LT3781 on the primary side to complete the 3.3V regulation. An LTC1693-1 high speed dual N-channel MOSFET driver provides the gate drive for the synchronous MOSFETs at the 3.3V output stage. The LTC1693-1 driver's input signals come from SG and BG outputs of the LT3781 through two small gate drive transformers (T2 and T3). The LT3804 also precisely regulates the 1.8V output by further reducing and controlling the duty cycle of the switching waveform from the power transformer (T1) secondary winding. In fact, the 1.8V circuit is a special synchronous buck converter whose input is a pulsed waveform instead of a DC voltage. True differential remote sensing is provided for both outputs to achieve high regulation accuracies. Power good indicator PGOOD will be high only if both outputs are within 10% of their nominal values. The LT3804 provides current limit function for both 1.8V and 3.3V outputs. The current limits for 3.3V and 1.8V outputs are estimated to be 50mV/R55 and 50mV/R49, respectively.
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LT3804
APPLICATIO S I FOR ATIO
A planar transformer PA0191 by Pulse Engineering is employed as the power transformer in this design. This transformer is constructed on a PQ20 core with nine turns of primary windings, two turns of secondary windings and seven turns of auxiliary windings for the LT3781 bias supply. Si7892DP MOSFETs are selected for the secondary side due to their low RDS (ON), 30V VDSS rating and compact, thermally enhanced PowerPak SO-8 package.
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The switching frequency of the circuit is about 230kHz. 1500V input to output isolation is provided. Additional features of this design include primary side on/off control, input over voltage protection, under voltage lockout, soft start and board over temperature shutdown. The complete design is mounted within a standard half brick PC board with about half inch height.
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Vi SEC
+VIN 36V TO 72V Q1 Si7456DP T1 PULSE PA0191 L3 1.8H CEP125-1R8 VO 1 CLIN VO 1 3.3V AT 15A R55 0.003 1% 2512 CLIP
L1 1.2H DO1813P-122HC
C2 1.5F 100V x2 D1 B2100 D1 B2100 Q4 Si7892DP x2 Q6 Si7892DP x2 R3 10 1/4W R4 10 1/4W R6 3.3 C8 1000pF 100V C9 1000pF 100V
Q3 Si7456DP
C4 470F 4V POSCAP x3
-VIN D3 BAS21TA C10 2200pF 250VAC C6 4.7F 25V VOUT D6 B340A Q12 FZT690B D12 V BAT54S CC VCCS C15 4.7F 16V R18 100 D18 B0540W L2, 1mH DO1608C-105 COILCRAFT VCC D4 BAS21TA D4 BAT54F R17 10k
R9, 0.015 1%,1/2W
R25 20k
Q7 FZT853
D19 5241B 11V
VCC
D20 B0540W R8 10 C20 0.1F 100V R30 1k R36 1k C17 0.1F SG 9 12 R29 1k Q10 ZVN3310F C14 330pF
R16 2k 0.25W D10 10V MMBZ5240B
C13 4.7F 25V
VCC
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C21 1F 16V R34 470
VCCS
R24 270k 0.25W
R26 73.2k 1%
D13 BAS21TA
C19 T3 0.1F P2033 PULSE ENG.
8 C33 10nF R33 6.8k D9 BAT54 R31 470
1
20 TG VBST BSTREF SENSE PGND LT3781 VFB BG
19 18
C1 0.01F 15 11 14
13
D17 MMBD4148 5VREF FSET THERM SYNC SS SGND VC
2
VCC
T2 C16 P2033 10nF PULSE ENG.
LTC1693-1 6 VCC2 VCC1 7 IN1 OUT1 3 5 IN2 OUT2 2 4 GND1 GND2
0VLO
ON OFF 5 5VREF C30 0.015F C29 0.01F RT1 100k R37 1k 6 3 7 8 4 10
1
SHDN
R38 1k ISO1 MOC207 7 5VREF 6 4 3 1
R32 6.8k R35 1k C22 4700pF
D8 BAT54
R43 10k R39 52.3k 1% R42 2.43k C32 1% 82pF
OPTO
C25 4.7F 16V
C27 1F
C28 1000pF
R45 1.24k C31 1% 1F
C26 6.8nF
R46 330 5 8 2
LT3804 TA02
LT3804
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Figure 4. 36V - 72VDC to 3.3V/15A and 1.8V/15A Dual Output Isolated Power Supply (Page 1 of 2)
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APPLICATIO S I FOR ATIO U W
(4TPD470M x3) VO RTN
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LT3804
APPLICATIO S I FOR ATIO
SEC FROM TRANSFORMER SECONDARY WINDING VCCS C45 10pF R57 10k C47 1F VCCS R5 100k PGOOD OPTO 23 19 16 7 CLIP C49, 1000pF CLIN C37, 680pF 1 2 22 R13 1.5k C50 1000pF 18 13 R65 10 VO1 C24 4.7nF VO1S+ R14 3.01k 1% R66 665 1% R15 3.01k 1% R67 665 1% R68 10 C51 R19 6.8nF 1k 10 28 8 SYNC OPTO LT3804 PGOOD BGS CSET CLIP CLIN VAOUT1 VFB1 GNDS1 PGIN1 ILCOMP1 TGATE SW BGATE CL2P CL2N VAOUT2 VFB2 GNDS2 PGIN2 ILCOMP2 SS2 9 C43 0.1F 25 VCC D14 4 CMDSH-3 27 5 6 26 20 21 15 14 12 11 3 R12 10k C48 180pF R53 220 C42 4700pF VO2S+ R54 3.01k 1% R60 1.5k 1% R62 3.01k 1% R61 1.5k 1% 1.8V OUTPUT REMOTE SENSE C39 330pF R50 3.3k C38 0.033F C46 1000pF Q14 Si7892DP x2 Q13 Si7892DP L4 1.8H CEP125-1R8 R49 0.003 1% R64 10 C36 C44 4.7F 0.1F 16V 16V C12 + 680F 2.5V POSCAP x3 D15 CMDSH-3 (2R5TPD680M x3)
BOOST GBAIS
3.3V OUTPUT REMOTE SENSE
R58 SS1 PGND 10k 17 24 C35 180pF
VO1S-
Figure 4. 36V - 72VDC to 3.3V/15A and 1.8V/15A Dual Output Isolated Power Supply (Page 2 of 2)
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+VO2 1.8V 15A VO2S- R63 10
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PACKAGE DESCRIPTIO U
FE Package 28-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation EB
4.75 (.187) 9.60 - 9.80* (.378 - .386) 4.75 (.187) 28 2726 25 24 23 22 21 20 19 18 1716 15 6.60 0.10 4.50 0.10 SEE NOTE 4 0.45 0.05
2.74 (.108)
EXPOSED PAD HEAT SINK ON BOTTOM OF PACKAGE
2.74 6.40 (.108) BSC
1.05 0.10 0.65 BSC RECOMMENDED SOLDER PAD LAYOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1.20 (.047) MAX 0 - 8
4.30 - 4.50* (.169 - .177)
0.09 - 0.20 (.0036 - .0079)
0.45 - 0.75 (.018 - .030)
0.65 (.0256) BSC
0.195 - 0.30 (.0077 - .0118)
0.05 - 0.15 (.002 - .006)
FE28 (EB) TSSOP 0203
NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE
4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE
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LT3804
RELATED PARTS
PART NUMBER LT1339 LT1425 LT1431 LT1680 LT1725 LT1737 LT1950 LT3710 LTC3722 LT3781 DESCRIPTION High Power Synchronous DC/DC Controller Isolated Flyback Switching Regulator Programmable Reference High Power DC/DC Step-Up Controller General Purpose Isolated Flyback Controller High Power Isolated Flyback Controller PWM Controller for Forward, Flyback, Boost and SEPIC Secondary Side Synchronous Post Regulator Synchronous Phase Modulated Full-Bridge Controller Dual Transistor Synchronous Forward Controller COMMENTS Operation Up to 60V Maximum General Purpose with External Application Resistor 0.4% Initial Voltage Tolerance Operation Up to 60V Maximum Drives External Power MOSFET with External ISENSE Resistor Sense Output Voltage Directly from Primary-Side Winding 3V VIN 25V, Volt-Second Clamp, Leading-Edge Blanking, Slope Compensation Generates Regulated Auxiliary Output in Isolated DC/DC Converters, Dual N-Channel MOSFET Synchronous Drivers Adaptive or Manual Delay Control for Zero Voltage Switching, Adjustable Maximum ZVS Delay, Current Mode and Voltage Mode. Operation Up to 72V Maximum
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
q
LT/TP 0603 1K * PRINTED IN USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2003

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